QUALCOMM Incorporated
HETEROGENEOUS HEIGHT LOGIC CELL ARCHITECTURE

Abstract:

A MOS IC includes first and second sets of adjacent transistor logic, each of which include collinear gate interconnects extending in a first direction with the same gate pitch. The first set of transistor logic has a first cell height h.sub.1 and a first number of M.sub.x layer tracks that extend unidirectionally in a second direction orthogonal to the first direction. The second set of transistor logic has a second cell height h.sub.2 and a second number of M.sub.x layer tracks that extend unidirectionally in the second direction, where h.sub.2>h.sub.1 and the second number of M.sub.x layer tracks is greater than the first number of M.sub.x layer tracks. At least one of a height ratio h.sub.R=h.sub.2/h.sub.1 is a non-integer value or a subset of the first set of transistor logic and a subset of the second set of transistor logic are within one logic cell.