QUALCOMM Incorporated
GATE-TO-CONTACT SHORT PREVENTION WITH AN INNER SPACER

Abstract:

Certain aspects of the present disclosure generally relate to a self-aligned contact with gate-to-contact short prevention in a multi-gate transistor structure, such as a multi-gate fin field-effect transistor (finFET) structure. An example multi-gate transistor structure includes a semiconductor fin, a first gate, a first spacer, a source or drain contact, and a first nonconductive liner. The first gate is disposed above and partially surrounds a portion of the semiconductor fin. The first spacer is located adjacent to a side of the first gate. The source or drain contact is coupled to a source or drain region of the semiconductor fin. The first nonconductive liner is disposed between the source or drain contact and the first spacer.