QUALCOMM Incorporated
Memory system design for signal integrity crosstalk reduction with asymmetry

Abstract:

An integrated circuit is described. The integrated circuit (IC) may include a printed circuit board (PCB). The IC may also include a system on chip (SoC) die on the PCB. The IC may further include a memory device coupled to a parallel memory interface of the SoC die. The memory device may be coupled to a parallel memory interface through parallel signal traces arranged in an asymmetric routing. In the asymmetric routing of the parallel signal traces, the signal traces are arranged according to a variable spacing is between the parallel signal traces for a majority portion of the parallel signal traces.