QUALCOMM Incorporated
Adaptive dynamic clock and voltage scaling

Last updated:

Abstract:

In each of two or more pipelined subsystems, the relative amount of time that the processing cores are idle may be determined. If the idle ratio is below a threshold, the clock frequency and voltage may be adjusted using dynamic clock and voltage scaling (DCVS) based on a power limit. However, if the idle ratio exceeds the threshold, the clock frequency and voltage may be decreased without regard to the power limit.

Status:
Grant
Type:

Utility

Filling date:

1 Apr 2021

Issue date:

20 Sep 2022