Rambus Inc.
Interface for memory readout from a memory component in the event of fault

Last updated:

Abstract:

Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) memory component is disclosed that includes a memory core, a primary interface, and a secondary interface. The primary interface includes data input/output (I/O) circuitry and control/address (C/A) input circuitry, and accesses the memory core during a normal mode of operation. The secondary interface accesses the memory core during a fault mode of operation.

Status:
Grant
Type:

Utility

Filling date:

22 Aug 2019

Issue date:

19 Apr 2022