Rambus Inc.
Memory component with input/output data rate alignment

Last updated:

Abstract:

First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

Status:
Grant
Type:

Utility

Filling date:

7 Jul 2017

Issue date:

2 Aug 2022