Rambus Inc.
Synchronous signaling interface with over-clocked timing reference

Last updated:

Abstract:

In a chip-to-chip signaling system includes at least one signaling link coupled between first and second ICs, the first IC has an interface coupled to the signaling link and timed by a first interface timing signal. The second IC has an interface coupled to the signaling link and timed by a second interface timing signal that is mesochronous with respect to the first interface timing signal. The second IC further has phase adjustment circuitry that adjusts a phase of the second interface timing signal using a digital counter implemented with Josephson-junction circuit elements.

Status:
Grant
Type:

Utility

Filling date:

24 Mar 2020

Issue date:

20 Sep 2022