Silicon Laboratories Inc.
State retention circuit that retains data storage element state during power reduction mode

Abstract:

A semiconductor device that retains a state of a data storage element during a power reduction mode including supply rails and voltages, and a storage latch and a retention latch both powered by retention supply voltage that remains energized during a power reduction mode. The storage latch and the retention latch are both coupled to a retention node that is toggled between first and second states before entering the power reduction mode. The toggling causes the storage latch to latch the state of the data storage element during the normal mode, and the retention node enables the storage element to hold the state during the power reduction mode. The retention latch includes a retention transistor and a retention inverter powered by the retention supply voltage. The retention inverter keeps the retention transistor turned on and the retention transistor holds the state of the retention node during the power reduction mode.