Silicon Laboratories Inc.
Apparatus with Electronic Circuitry Having Reduced Leakage Current and Associated Methods

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Abstract:

An apparatus includes an integrated circuit (IC), which includes complementary metal oxide semiconductor (CMOS) circuitry. The CMOS circuitry includes a p-channel transistor network that includes at least one p-channel transistor having a gate-induced drain leakage (GIDL) current. The IC further includes a native metal oxide semiconductor (MOS) transistor coupled to supply a bias voltage to the at least one p-channel transistor to reduce the GIDL current of the at least one p-channel transistor.

Status:
Grant
Type:

Utility

Filling date:

31 Mar 2020

Issue date:

20 Aug 2020