Synopsys, Inc.
Power Estimation System

Abstract:

A method of power test analysis for an integrated circuit design including loading test vectors into a first sequence of flip-flops in scan mode, evaluating the test vectors and saving results of the evaluating in a second sequence of flip-flops in scan mode, reading results out of the second sequence of flip-flops to a scan chain, and calculating power generation based on the results. In one embodiment, the test vectors are received from an automatic test pattern generator.