Synopsys, Inc.
CIRCUIT LAYOUT VERIFICATION

Abstract:

A system, method, and computer readable medium with instructions for verifying an original layout are disclosed. The original layout includes cells arranged in a cell hierarchy, front-end-of-line (FEOL) layers, and back-end-of-line (BEOL) layers. In one embodiment, a reduced layout is generated by trimming out cells below a top tier of the cell hierarchy and filtering out the FEOL layers. A text-based short check is executed on the reduced layout. Next, an augmented reduced layout is generated. The augmented reduced layout includes pin information for cells in a second tier connected to the top tier. An interconnectivity check is then executed on the augmented reduced layout based on a schematic for the circuit. Afterwards, a result (e.g., location of short or connectivity mismatch) based on at least one of the text-based short check and the interconnectivity check is outputted. A conventional LVS check may then be executed.