Synopsys, Inc.
Method and apparatus for reducing pessimism of graph based static timing analysis

Abstract:

Disclosed is a method and apparatus that takes timing information associated with a plurality of inputs to a cell, such as an AND-gate, within an integrated circuit (IC) design, store the timing information in a timing information register (TIR) associated with an index identifying the source of the timing information and track the source of the timing information for a predetermined number of cells through the index. The timing information in the TIRs is merged upon the index indicating that the timing information has been tracked through a predetermined number of cells.