Synopsys, Inc.
MEMORY EFFICIENT SCALABLE DISTRIBUTED STATIC TIMING ANALYSIS USING STRUCTURE BASED SELF-ALIGNED PARALLEL PARTITIONING

Abstract:

A method includes extracting information associated with constraints and clock information from a file of a circuit design; determining a topological cone based on the extracted information for a partition of two or more partitions of the circuit design, and performing timing analysis on the partition of the two or more partitions based on the topological cone. The topological cone includes objects associated with the partition of the two or more partitions of the circuit design.