Synopsys, Inc.
Drift tracking using an analog delay line during clock-data recovery

Last updated:

Abstract:

A clock recovery circuit may include a first circuit to produce an output signal that is a logical combination of an edge detection signal and a clock signal. At least some transitions in the edge detection signal may correspond to transitions in a set of data signals. The clock recovery circuit may also include a second circuit to average the output signal to produce a voltage, and a third circuit to add a variable delay to the clock signal based on the voltage.

Status:
Grant
Type:

Utility

Filling date:

6 Aug 2020

Issue date:

23 Aug 2022