Synopsys, Inc.
AUTOMATED DESIGN HIERARCHY IDENTIFICATION AND SIMPLIFIED REDUCED MODEL GENERATION FOR STATIC VERIFICATION OF CIRCUIT DESIGNS

Abstract:

A system performs efficient verification of a circuit design. The system receives a circuit design including circuit blocks. The system identifies some of the circuit blocks as modeled circuit blocks. The system generates simplified reduced models (SRMs) for the modeled circuit blocks. A simplified reduced model includes circuit details sufficient for static verification of the circuit design but excludes some of the circuit details for the modeled circuit block. The system performs static verification of the circuit design using the simplified reduced models.