Synopsys, Inc.
ENHANCED READ SENSING MARGIN FOR SRAM CELL ARRAYS

Abstract:

This disclosure describes a memory cell array with enhanced read sensing margin. The memory cell array includes a write port and a read port being connected through first and second data storage lines. The memory cell array further includes multiple word lines and bit lines arranged in rows and columns such that the read port is coupled to a read word line, a read bit line, and a virtual ground. The read port includes a first transistor coupled to at least the read bit line and the virtual ground, a second transistor coupled to at least the first data storage line and the first transistor, a third transistor coupled to at least the second data storage line and the read word line, and a fourth transistor coupled at least the first data storage line and the read word line.