Synopsys, Inc.
ONE TIME PROGRAMMABLE (OTP) BIT CELL WITH INTEGRATED INHIBIT DEVICE

Abstract:

A one-time programmable (OTP) memory device includes a memory array having multiple memory elements. The memory array includes a plurality of anti-fuse FinFETs and a plurality of access FinFETs. Each anti-fuse device has a first terminal for receiving a programming voltage and a second terminal. The anti-fuse FinFETs are located in a first region of an integrated circuit. At least one anti-fuse FinFET of the plurality of anti-fuse FinFETs and at least one access FinFET of the plurality of access FinFETs form a memory element of the plurality of memory elements of the memory array. Each access FinFET is configured to selectively couple one of a program inhibit voltage and a program enable voltage to the second terminal of a corresponding anti-fuse FinFET in a programming operation. The access FinFETs are located in a second region of the integrated circuit, different than the first region of the integrated circuit.