Synopsys, Inc.
MEMORY ARRAY ARCHITECTURES FOR MEMORY QUEUES

Abstract:

Memory queues described herein use a single hardware and/or software architecture for a memory array. This memory array can be partitioned to be between one memory sub-array to implement a single memory queue and multiple memory sub-arrays to implement multiple memory queues. Various electrical signals provided by or provided to these multiple memory queues include addressing information to associate these various control signals with one or more of the multiple memory sub-arrays. In some situations, the memory queues can externally associate their corresponding read pointers to entries of one of their memory sub-arrays. In these situations, these memory queues can dynamically associate their read pointers to point to any entry from among their memory arrays and to read the data store therein starting from any random entry within their memory arrays.