Synopsys, Inc.
Bit-line repeater insertion architecture

Abstract:

An SRAM architecture to optimize the performance of the SRAM. The local bit-lines are activated one at a time with control signals from a decoder. The global bit-lines are broken with repeaters to optimize performance. This guarantees optimal performance for the SRAM array across a wide range of supply voltages spanning from the nominal voltage of a process to a sub-threshold range.