Synopsys, Inc.
Optimization after allocating potential slacks to clock arrival times

Abstract:

During logic synthesis and placement optimization, designs are aggressively optimized for timing, power, and area but only the data paths are modified and the clock network is assumed to be "ideal" and fixed. The described embodiments optimize the clock network as well as the data path logic during the logic synthesis and placement optimization stages, thereby improving the overall performance of the design.