Synopsys, Inc.
Phase-locked loop (PLL) with calibration circuit

Abstract:

A phase-locked loop (PLL) for generating a VCO output signal at a target frequency has been disclosed. The PLL includes at least first and second VCOs, first and second multiplexers, and a frequency divider. The first and second VCOs generate first and second output signals over first and second frequency ranges, respectively. The first multiplexer receives the first and second output signals from the first and second VCOs, respectively, and outputs the first output signal when the target frequency is in the first frequency range and the second output signal when the target frequency is in the second frequency range or less than the first frequency range. The frequency divider divides a frequency of the second output signal by a division factor to generate a third output signal. The second multiplexer outputs one of the first, second, and third output signals as the VCO output signal.