Synopsys, Inc.
Fast locking clock and data recovery circuit

Abstract:

A clock and data recovery circuit includes a bang-bang phase detector (BBPD), a voltage controlled oscillator (VCO), a frequency control circuit, and an up-down counter. The BBPD generates an early-late signal by determining whether serialized data received by the BBPD is early or late with respect to a VCO clock signal generated by the VCO. A phase of the VCO clock signal is controlled based on the early-late signal. The frequency control circuit compares a frequency of the VCO clock signal and a target frequency and generates an up/down signal. Based on the up/down signal, the up-down counter increments or decrements the frequency of the VCO clock signal to match the target frequency.