Synopsys, Inc.
Virtual cell model usage

Abstract:

Hierarchical design levels describe semiconductor designs and define architecture, behavior, structure, function, etc. for the designs. A virtual cell model based on cells populating a design is constructed and used for purposes including design simulation, analysis, verification, validation, and so on. A cell and multiple instances of the cell are identified across a design. An empty cell model comparable to the identified cell is created. A compressed representation of unsolved geometric data based on the identified cell data and a virtual hierarchical layer (VHL) are generated as model data, and the model data is placed into the empty cell model. As a result of the placement of the model data, a virtual cell model is created.