Synopsys, Inc.
Force/release support in emulation and formal verification

Abstract:

Forming a logic circuit design from a behavioral description language that includes N force and M release statements applied to a net disposed in the design, includes, in part, forming N multiplexers and a controller controlling the select terminals of the N multiplexers. Each multiplexer receives a force signal at its first input terminal. The output signal of the i.sup.th multiplexer is supplied to a second input terminal of (i+1).sup.th multiplexer. A driver signal driving the net in the absence of the force statements is applied to a second input terminal of a first multiplexer. The controller asserts the select signal of the i.sup.th multiplexer if the i.sup.th force condition is active, and unasserts the select signal of the i.sup.th multiplexer if any one of a number of predefined conditions is satisfied.