Synopsys, Inc.
Deep insight for debug using internal equivalence visualization and counter-example for sequential equivalence checking

Abstract:

Disclosed is a technology for parallelized design verification of two circuit designs at a register transfer level. A plurality of potential equivalent sub-circuit pairs is identified from the circuit designs to create a proof-tree structure. The proof-tree structure includes a root-proof, a plurality of parent-proofs downchain of said root-proof and a plurality of child-proofs downchain of at least one of the parent-proofs. Each one of the child-proofs is associated with a first equivalency status of one of the potential equivalent sub-circuit pairs. The parent-proofs are associated with second equivalency statuses dependent upon the first equivalency statuses of downchain child-proofs. The root-proof is associated with a third functional equivalency status of the two circuit designs dependent upon the second equivalency statuses of downchain parent-proofs. This Abstract is not intended to limit the scope of the claims.