Synopsys, Inc.
Mitigating write disturbance in dual port 8T SRAM

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Abstract:

The independent claims of this patent signify a concise description of embodiments. Disclosed is technology for reducing write disturbance while writing data into a first SRAM cell and accessing a second SRAM cell in a row of SRAM cells. This Abstract is not intended to limit the scope of the claims.

Status:
Grant
Type:

Utility

Filling date:

25 Oct 2018

Issue date:

17 Dec 2019