Synopsys, Inc.
Pessimism reduction in static timing analysis

Abstract:

A method for performing graph-based static timing analysis comprises reading in a design of an integrated circuit having a subset of timing paths, each timing path of the subset having a common point, wherein the common point is identical for all timing paths of the subset. The method comprises initiating a timing signal at the common point, the timing signal propagating along a plurality of timing arcs of the subset. The timing signal has a plurality of attributes varying with the propagation including a depth value and/or a distance value. The method comprises determining a derating factor for a delay of at least one of the plurality of timing arcs depending on the depth and/or the distance value of the timing signal at a pin of said at least one timing arc, and generating a timing report based on the derating factor.