Sony Group Corporation
ARITHMETIC APPARATUS AND MULTIPLY-ACCUMULATE SYSTEM

Abstract:

An arithmetic apparatus includes first and second arithmetic circuit units. Multiply-accumulate signals output from a plurality of output lines of the first arithmetic circuit unit or signals generated on the basis of the multiply-accumulate signals are input into a plurality of input lines of the second arithmetic circuit unit. An extending direction of the plurality of input lines of the first arithmetic circuit unit and an extending direction of the plurality of output lines of the second arithmetic circuit unit are parallel to each other. Assuming that end portions of two endmost output lines of the first arithmetic circuit unit are defined as first and second end portions and end portions of two endmost input lines of the second arithmetic circuit unit are defined as third and fourth end portions, the end portions of the two endmost output lines being located on a side of the second arithmetic circuit unit, the end portions of the two endmost input lines being located on a side of the first arithmetic circuit unit, a position in the first direction of at least one of the first or second end portion a position between a position of the third end portion a position of the fourth end portion. Or, a position in the first direction of at least one of the third or the fourth end portion is between a position of the first end portion and a position of the second end portion.