Synaptics Incorporated
Phase locked loop sampler and restorer

Abstract:

Systems, methods, and apparatus for a circuit for synchronization of a reference signal and an output signal of a phased-lock loop (PLL) are disclosed. The method comprises continuously generating, by a clock detect circuit connected to the PLL, a clock detect signal indicating whether the reference signal of the PLL is present or lost. The method further comprises continuously sampling and storing, by a loop sampler circuit connected to the PLL, a voltage from a loop filter of the PLL, when the reference signal is present. In addition, the method comprises configuring a charge pump of the PLL into a high impedance state, thereby disabling the charge pump, when the clock detect signal indicates that the reference signal is lost. Further, the method comprises supplying the voltage to the PLL to maintain a frequency of the output signal of the PLL, when the reference signal is lost.