Synaptics Incorporated
Hierarchical gate line driver

Abstract:

A hierarchical gate driver circuit for an array of pixel elements. The hierarchical gate driver circuit includes a shift register and two or more groups of gate lines drivers. The shift register is configured to activate a plurality of select lines based at least in part on a periodic clock signal. A first group of gate line drivers is configured to drive a plurality of first gate lines, each coupled to a respective row of first pixel elements in the array, when a first select line of the plurality of select lines is activated. A second group of gate line drivers is configured to drive a plurality of second gate lines, each coupled to a respective row of second pixel elements in the array, when a second select line of the plurality of select lines is activated.