Taiwan Semiconductor Manufacturing Company Limited
Self Timed Level Shifter Circuit

Abstract:

Systems and methods are provided for a level shifter. A level shifter includes a network of transistors configured to receive a signal at a first node in a first voltage domain and to generate a corresponding signal at a second node in a second voltage domain during a transition period of time. A self timing circuit is configured to receive an initiation signal based on the signal at the first node and to generate a voltage transition accelerator signal that is used to pull up the second node prior to the expiration of the transition period of time.