Taiwan Semiconductor Manufacturing Company Limited
MEMORY DEVICE WITH FLAT-TOP BOTTOM ELECTRODES AND METHODS FOR FORMING THE SAME

Abstract:

A memory device including an array of memory cells overlying a substrate and located in a memory array region. Each of the memory cells includes a vertical stack containing a bottom electrode, a memory element, a top electrode, and dielectric sidewall spacers located on sidewalls of each vertical stack. The bottom electrode comprises a flat-top portion that extends horizontally beyond an outer periphery of the dielectric sidewall spacers. The device also includes a discrete etch stop dielectric layer over each of the memory cells that includes a horizontally-extending portion that extends over the flat-top portion of the bottom electrode. The device also includes metallic cell contact structures that contact a respective subset of the top electrodes and a respective subset of vertically-protruding portions of the discrete etch stop dielectric layer.