Texas Instruments Incorporated
Enabling high at-speed test coverage of functional memory interface logic by selective usage of test paths

Abstract:

A device to test functional memory interface logic of a core under test is described herein. The device includes and utilizes a built in self test controller to generate test sequences, and a clock-gating circuit to selectively supply the test sequences to a memory input or memory output on the core under test. After an initial data initialization of the core under test at built in self test mode, an at-speed functional mode is utilized to capture a desired memory output.