Texas Instruments Incorporated
FET USING TRENCH ISOLATION AS THE GATE DIELECTRIC

Abstract:

A semiconductor device includes a Silicon-on-Insulator (SOI) substrate including a top device layer, a buried oxide (BOX) layer, and a bottom handle portion. A filled trench is lined with a trench dielectric layer that extends to at least the BOX layer, defining an inner and an outer portion of the device layer. A field effect transistor (FET) includes an inner portion, a source region having a source contact thereto and a drain region having a drain contact thereto, each doped a first doping type. A gate region has a gate contact that is separated from the inner portion by the trench dielectric. The source and drain region are separated by a body region doped a second doping type having a body contact.