VMware, Inc.
Supporting PCI-e message-signaled interrupts in computer system with shared peripheral interrupts

Abstract:

A method of handling message signaled interrupts in a computer system that uses an internal bus for communication between peripheral devices, using shared peripheral interrupt (SPI) vectors. The method includes determining whether a message signaled interrupt (MSI) needs to be allocated for a PCI-e device for an interrupt to be sent to a host. If it is determined that MSI needs to be allocated for the PCI-e device, a determination is made as to whether a Locality Specific Interrupt (LPI) register or an Interrupt Translation Service (ITS) is available to process the interrupt. If it is determined that neither the LPI register nor the Interrupt Translation Service (ITS) is available to process the interrupt, the PCI-e device is configured for SPI-based MSI generation to route the interrupt by determining an available SPI vector and assigning the available SPI vector to the PCI-e device.