Apple Inc.
Electronic devices with crest factor reduction circuitry

Abstract:

An electronic device may include a baseband processor and P antenna elements. The antenna elements may concurrently convey signals within M signal beams. The baseband processor may have a demultiplexer that receives a stream of M symbols. The processor may have M parallel data paths coupled between the demultiplexer and a beam former. The beam former may be coupled to amplifier circuitry over P parallel data paths. Inverse fast Fourier transformers (IFFTs) may be interposed on the M parallel data paths. A feedback path may be coupled between the M parallel data paths and the P parallel data paths. Crest factor reduction (CFR) circuitry may be interposed on the feedback path. The CFR circuitry may perform CFR operations on signals from the P parallel data paths iteratively and concurrently. This may minimize PAR in the system while supporting concurrent transmission of radio-frequency signals in multiple signal beams.