Apple Inc.
Selection of instructions to issue in a processor

Abstract:

Techniques are disclosed relating to selection circuitry configured to select instruction operations to issue to one or more execution circuits of a processor. In some embodiments, an apparatus includes a plurality of execution circuits configured to perform one or more instruction operations. The apparatus may further include a plurality of instruction queues configured to store information indicative of the one or more instruction operations. In some embodiments, the apparatus may include a selection circuit configured to select a first plurality of instruction operations from a first instruction queue. The selection circuit may be configured to select a first instruction operation from the first plurality of instruction operations to issue to a first execution circuits. Further, the selection circuit may be configured to select a predesignated instruction operation of the first plurality of instruction operations to issue to a second execution circuit in response to a determination that no instruction operations in a second instruction queue are available to issue.