Apple Inc.
SCHEDULING OF READ AND WRITE MEMORY ACCESS REQUESTS

Abstract:

A memory system includes a memory circuit including a plurality of pages, including a particular page having a page activation time. The memory system also includes a memory controller circuit configured to receive a memory access request corresponding to data of the particular page. The memory controller circuit is also configured to transmit, in response to a determination that the particular page is inactive, an activation command to the memory circuit to activate the particular page, and to schedule a future transmission of an initial memory command for the particular page based on the page activation time.