Kulicke and Soffa Industries, Inc.
Methods for generating wire loop profiles for wire loops, and methods for checking for adequate clearance between adjacent wire loops
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Abstract:
A method of generating a wire loop profile in connection with a semiconductor package is provided. The method includes the steps of: (a) providing package data related to the semiconductor package; and (b) creating a loop profile of a wire loop of the semiconductor package, the loop profile including a tolerance band along at least a portion of a length of the wire loop.
Status:
Grant
Type:
Utility
Filling date:
22 Apr 2020
Issue date:
29 Mar 2022