Microsoft Corporation
REACH MATRIX SCHEDULER CIRCUIT FOR SCHEDULING OF INSTRUCTIONS TO BE EXECUTED IN A PROCESSOR

Abstract:

A reach matrix scheduler circuit for scheduling instructions to be executed in a processor is disclosed. The scheduler circuit includes an N.times.R matrix wake-up circuit, where `N` is the instruction window size of the scheduler circuit, and `R` is the "reach" with the instruction window of matrix wake-up circuit, with `R` being less than `N`. A grant line associated with each instruction request entry in the N.times.R matrix wake-up circuit is coupled to `R` other instruction entries among the `N` instruction entries. When a producer instruction in an instruction request entry is ready for issuance, the grant line associated with the instruction request entry is activated so that any other instruction entries coupled to the grant line (i.e., within the "reach" of the instruction request entry) that consume the produced value generated by the producer instruction are "woken-up" and subsequently indicated as ready to be issued.