Microsoft Corporation
METHOD TO OVERLOAD HARDWARE PIN FOR IMPROVED SYSTEM MANAGEMENT

Abstract:

A computer system includes a host processor including a hardware interrupt pin. The computer system also includes host firmware including an interrupt handler. The interrupt handler includes a plurality of sets of instructions that are executable by the host processor. The computer system also includes a baseboard management controller (BMC) that is connected to the hardware interrupt pin. The BMC is configured to generate an interrupt signal on the hardware interrupt pin in response to occurrence of a triggering event. The BMC is also configured to provide the host processor with context information that identifies a set of instructions in the host firmware that should be executed in response to the interrupt signal.