Microsoft Corporation
BANKED MEMORY ARCHITECTURE FOR MULTIPLE PARALLEL DATAPATH CHANNELS IN AN ACCELERATOR

Abstract:

The present disclosure relates to devices and methods for using a banked memory structure with accelerators. The devices and methods may segment and isolate dataflows in datapath and memory of the accelerator. The devices and methods may provide each data channel with its own register memory bank. The devices and methods may use a memory address decoder to place the local variables in the proper memory bank.