Atomera Incorporated
Utility Patents

Last updated:

List of all Atomera Incorporated patents 49 in total

Status Patent
Grant
Utility: Bipolar junction transistors including emitter-base and base-collector superlattices External link
Filling date: 6 Sep 2025 Issue date: 6 Sep 2022
Grant
Utility: Methods for making bipolar junction transistors including emitter-base and base-collector superlattices External link
Filling date: 6 Sep 2025 Issue date: 6 Sep 2022
Grant
Utility: Method for making superlattice structures with reduced defect densities External link
Filling date: 6 Sep 2025 Issue date: 30 Aug 2022
Grant
Utility: Vertical semiconductor device with enhanced contact structure and associated methods External link
Filling date: 6 Sep 2025 Issue date: 12 Jul 2022
Grant
Utility: Method for making semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice External link
Filling date: 6 Sep 2025 Issue date: 7 Jun 2022
Grant
Utility: Semiconductor device including a superlattice and an asymmetric channel and related methods External link
Filling date: 6 Sep 2025 Issue date: 10 May 2022
Grant
Utility: Method for making semiconductor device including a superlattice with different non-semiconductor material monolayers External link
Filling date: 6 Sep 2025 Issue date: 12 Apr 2022
Grant
Utility: Semiconductor devices including hyper-abrupt junction region including spaced-apart superlattices and related methods External link
Filling date: 6 Sep 2025 Issue date: 23 Nov 2021
Grant
Utility: Semiconductor device including a superlattice with different non-semiconductor material monolayers External link
Filling date: 6 Sep 2025 Issue date: 16 Nov 2021
Grant
Utility: Method for making a semiconductor device including a superlattice and an asymmetric channel and related methods External link
Filling date: 6 Sep 2025 Issue date: 17 Aug 2021
Grant
Utility: Method for making a semiconductor device including a superlattice within a recessed etch External link
Filling date: 6 Sep 2025 Issue date: 27 Jul 2021
Grant
Utility: Method for making a varactor with a hyper-abrupt junction region including spaced-apart superlattices External link
Filling date: 6 Sep 2025 Issue date: 2 Mar 2021
Grant
Utility: Method for making semiconductor devices with hyper-abrupt junction region including spaced-apart superlattices External link
Filling date: 6 Sep 2025 Issue date: 2 Mar 2021
Grant
Utility: Semiconductor device including vertically integrated optical and electronic devices and comprising a superlattice External link
Filling date: 6 Sep 2025 Issue date: 5 Jan 2021
Grant
Utility: Method for making a semiconductor device having a hyper-abrupt junction region including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 29 Dec 2020
Grant
Utility: Method for making a semiconductor device including enhanced contact structures having a superlattice External link
Filling date: 6 Sep 2025 Issue date: 29 Dec 2020
Grant
Utility: Method for making a varactor with hyper-abrupt junction region including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 15 Dec 2020
Grant
Utility: Method for making a FINFET including source and drain dopant diffusion blocking superlattices to reduce contact resistance External link
Filling date: 6 Sep 2025 Issue date: 1 Dec 2020
Grant
Utility: Semiconductor device including body contact dopant diffusion blocking superlattice having reduced contact resistance External link
Filling date: 6 Sep 2025 Issue date: 24 Nov 2020
Grant
Utility: Varactor with hyper-abrupt junction region including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 17 Nov 2020
Grant
Utility: Method for making a FINFET having reduced contact resistance External link
Filling date: 6 Sep 2025 Issue date: 17 Nov 2020
Grant
Utility: Semiconductor device with metal-semiconductor contacts including oxygen insertion layer to constrain dopants and related methods External link
Filling date: 6 Sep 2025 Issue date: 17 Nov 2020
Grant
Utility: Method for making semiconductor device including body contact dopant diffusion blocking superlattice to reduce contact resistance External link
Filling date: 6 Sep 2025 Issue date: 17 Nov 2020
Grant
Utility: Varactor with hyper-abrupt junction region including spaced-apart superlattices External link
Filling date: 6 Sep 2025 Issue date: 3 Nov 2020
Grant
Utility: Semiconductor devices including hyper-abrupt junction region including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 3 Nov 2020
Grant
Utility: Method for making semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance External link
Filling date: 6 Sep 2025 Issue date: 27 Oct 2020
Grant
Utility: Method for making superlattice structures with reduced defect densities External link
Filling date: 6 Sep 2025 Issue date: 20 Oct 2020
Grant
Utility: Semiconductor device including enhanced contact structures having a superlattice External link
Filling date: 6 Sep 2025 Issue date: 15 Sep 2020
Grant
Utility: Inverted T channel field effect transistor (ITFET) including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 1 Sep 2020
Grant
Utility: Method for making a semiconductor device including non-monocrystalline stringer adjacent a superlattice-sti interface External link
Filling date: 6 Sep 2025 Issue date: 11 Aug 2020
Grant
Utility: Method for making a semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice External link
Filling date: 6 Sep 2025 Issue date: 28 Jul 2020
Grant
Utility: Method for making DRAM with recessed channel array transistor (RCAT) including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 28 Apr 2020
Grant
Utility: CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 7 Apr 2020
Grant
Utility: Method for making CMOS image sensor including stacked semiconductor chips and readout circuitry including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 31 Mar 2020
Grant
Utility: Method for making CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 31 Mar 2020
Grant
Utility: Method for making a semiconductor device having reduced contact resistance External link
Filling date: 6 Sep 2025 Issue date: 17 Mar 2020
Grant
Utility: FINFET including source and drain regions with dopant diffusion blocking superlattice layers to reduce contact resistance External link
Filling date: 6 Sep 2025 Issue date: 3 Mar 2020
Grant
Utility: Semiconductor device including source/drain dopant diffusion blocking superlattices to reduce contact resistance External link
Filling date: 6 Sep 2025 Issue date: 3 Mar 2020
Grant
Utility: Semiconductor device including superlattice structures with reduced defect densities External link
Filling date: 6 Sep 2025 Issue date: 18 Feb 2020
Grant
Utility: Method for making CMOS image sensor including pixels with read circuitry having a superlattice External link
Filling date: 6 Sep 2025 Issue date: 7 Jan 2020
Grant
Utility: CMOS image sensor including pixels with read circuitry having a superlattice External link
Filling date: 6 Sep 2025 Issue date: 7 Jan 2020
Grant
Utility: Semiconductor device including compound semiconductor materials and an impurity and point defect blocking superlattice External link
Filling date: 6 Sep 2025 Issue date: 5 Nov 2019
Grant
Utility: Method for making CMOS image sensor including photodiodes with overlying superlattices to reduce crosstalk External link
Filling date: 6 Sep 2025 Issue date: 29 Oct 2019
Grant
Utility: Semiconductor device including resonant tunneling diode structure having a superlattice External link
Filling date: 6 Sep 2025 Issue date: 22 Oct 2019
Grant
Utility: Semiconductor device including a superlattice as a gettering layer External link
Filling date: 6 Sep 2025 Issue date: 10 Sep 2019
Grant
Utility: Method for making CMOS image sensor with buried superlattice layer to reduce crosstalk External link
Filling date: 6 Sep 2025 Issue date: 27 Aug 2019
Grant
Utility: Method for making a semiconductor device including a superlattice as a gettering layer External link
Filling date: 6 Sep 2025 Issue date: 13 Aug 2019
Grant
Utility: Semiconductor device with recessed channel array transistor (RCAT) including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 30 Jul 2019
Grant
Utility: CMOS image sensor including stacked semiconductor chips and image processing circuitry including a superlattice External link
Filling date: 6 Sep 2025 Issue date: 30 Jul 2019

Showing 1 to 49 of 49 patents.